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[1.5×2=3 points] What is the benefit of using a virtual machine in the following scenarios:

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[CMPUT 466/566] Machine learning Coding Assignment 1

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[CMPUT 466/566] Machine learning Coding Assignment 2

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[CSE 546] Cloud Computing Project 1 (Part-I): IaaS

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[CSEG483/CSE5483] HW 1: 간단한 reduction 응용

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[CSEG483/CSE5483] HW 2: Matrix Multiplication

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[CSEG483/CSE5483] HW 3: Shared Memory를사용한 2D Image Processing

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$\rresponding state machine. We recommend that you still have two separate modules for the datapath and the control just to help you understand the separation of what is in a datapath and what is in a controller. In Part II, the control logic just generated control signals that were inputs to the datapath. In this part, you will see that there is a signal that needs to go from the datapath into the controller so make sure you account for it accordingly. Division in hardware is the most complex of the four basic arithmetic operations. Add, subtract and multiply are much easier to build in hardware. For this part, you will be designing a 4-bit restoring divider using a nite state machine. Figure 5 shows an example of how the restoring divider works. This mimics what you do when you do long division by hand. In this speci c example, number 7 (Dividend) is divided by number 3 (Divisor). The restoring divider starts with Register A set to 0. The Dividend is shifted left and the bit shifted out of the left most bit of the Dividend (called the most 11 signi cant bit or MSB) is shifted into the least signi cant bit (LSB) of Register A as shown in Figure 6. The Divisor is then subtracted from Register A. If the MSB of Register A is a 1, then we restore Register A back to its original value by adding the Divisor back to Register A, and set the LSB of the Dividend to 0. Else, we do not perform the restoring addition and immediately set the LSB of the Dividend to 1. You may use the subtract ( ) and addition (+) operators in Verilog to perform the subtraction and addition. The 1 in the MSB of Register A means that the value in Register A after the subtraction is a negative number, meaning that the Divisor is larger than the original value in Register A. That is why Register A is restored by adding back the Divisor. This sequence of steps is performed until all the bits of the Dividend have been shifted out. Once the process is complete, the new value of the Dividend register is the Quotient, and Register A will hold the value of the Remainder. 5.1 What to Do The top-level module of your design should have the following declaratiClockonle part3(, Resetn, G: modu$

\rresponding state machine. We recommend that you still have two separate modules for the datapath and the control just to help you understand the separation of what is in a datapath and what is in a controller. In Part II, the control logic just generated control signals that were inputs to the datapath. In this part, you will see that there is a signal that needs to go from the datapath into the controller so make sure you account for it accordingly. Division in hardware is the most complex of the four basic arithmetic operations. Add, subtract and multiply are much easier to build in hardware. For this part, you will be designing a 4-bit restoring divider using a nite state machine. Figure 5 shows an example of how the restoring divider works. This mimics what you do when you do long division by hand. In this speci c example, number 7 (Dividend) is divided by number 3 (Divisor). The restoring divider starts with Register A set to 0. The Dividend is shifted left and the bit shifted out of the left most bit of the Dividend (called the most 11 signi cant bit or MSB) is shifted into the least signi cant bit (LSB) of Register A as shown in Figure 6. The Divisor is then subtracted from Register A. If the MSB of Register A is a 1, then we restore Register A back to its original value by adding the Divisor back to Register A, and set the LSB of the Dividend to 0. Else, we do not perform the restoring addition and immediately set the LSB of the Dividend to 1. You may use the subtract ( ) and addition (+) operators in Verilog to perform the subtraction and addition. The 1 in the MSB of Register A means that the value in Register A after the subtraction is a negative number, meaning that the Divisor is larger than the original value in Register A. That is why Register A is restored by adding back the Divisor. This sequence of steps is performed until all the bits of the Dividend have been shifted out. Once the process is complete, the new value of the Dividend register is the Quotient, and Register A will hold the value of the Remainder. 5.1 What to Do The top-level module of your design should have the following declaratiClockonle part3(, Resetn, G: modu

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• Goal The default CPU scheduling algorithm of Nachos is a simple round-robin scheduler with 100 ticks time quantum. The goal of this MP is to replace it with a multilevel feedback queue, and understand the implementation of process lifecycle management and context switch mechanism. • Assignment • Trace code: Explain the purposes and details of the following 6 code paths to understand how nachos manages the lifecycle of a process (or thread) as described in the Diagram of Process State in our lecture slides (chp.3 p.8). 1-1. New→Ready Kernel::ExecAll() ↓ Kernel::Exec(char*) ↓ Thread::Fork(VoidFunctionPtr, void*) ↓ Thread::StackAllocate(VoidFunctionPtr, void*) ↓ Scheduler::ReadyToRun(Thread*) 1-2. Running→Ready Machine::Run() ↓ Interrupt::OneTick() ↓ Thread::Yield() ↓ Scheduler::FindNextToRun() ↓ Scheduler::ReadyToRun(Thread*) ↓ Scheduler::Run(Thread*, bool) 1-3. Running→Waiting (Note: only need to consider console output as an example) SynchConsoleOutput::PutChar(char) ↓ Semaphore::P() ↓ List::Append(T) ↓ Thread::Sleep(bool) ↓ Scheduler::FindNextToRun() ↓ Scheduler::Run(Thread*, bool) 1-4. Waiting→Ready (Note: only need to consider console output as an example) Semaphore::V() ↓ Scheduler::ReadyToRun(Thread*) 1-5. Running→Terminated (Note: start from the Exit system call is called) ExceptionHandler(ExceptionType) case SC_Exit ↓ Thread::Finish() ↓ Thread::Sleep(bool) ↓ Scheduler::FindNextToRun() ↓ Scheduler::Run(Thread*, bool) 1-6. Ready→Running Scheduler::FindNextToRun() ↓ Scheduler::Run(Thread*, bool) 2.5↓ SWITCH(Thread*, Thread*) ↓ (depends on the previous process state, e.g., [New,Running,Waiting]→Ready) ↓ for loop in Machine::Run() Note: switch.S contains the instructions to perform context switch. You must understand and describe the purpose of these instructions in your report. (You can try to understand the x86 instructions first. Appendix C and the MIPS version equivalent to x86 can get a lot of help.) • Implementation 2-1. Implement a multilevel feedback queue scheduler with aging mechanism as described below: (a) There are 3 levels of queues: L1, L2 and L3. L1 is the highest level queue, and L3 is the lowest level queue. (b) All processes must have a valid scheduling priority between 0 to 149. Higher value means higher priority. So 149 is the highest priority, and 0 is the lowest priority. (c) A process with priority between 0 – 49 is in the L3 queue, priority between 50 – 99 is in the L2 queue, and priority between 100 – 149 is in the L1 queue. (d) The L1 queue uses preemptive SJF (shortest job first) scheduling algorithm. If the current thread has the lowest approximated remaining burst time, it should not be preempted by the other threads in the ready queue. The burst time (job execution time) is approximated using the equation: ti = 0.5 * T + 0.5 * ti-1 (type double) , i > 0 , t0 = 0 Where T is the total running ticks within a CPU burst and the NachOS kernel statistic can be used to calculate the ticks. Update the approximated burst time when the thread becomes waiting state, stop accumulating T when the thread becomes ready state, and resume accumulating T when the thread moves back to the running state. If there is any ready thread with the approximated remaining burst time lower than the current thread, the current thread should be preempted. The approximated remaining burst time can be calculated by the approximated burst time minus its running burst time T. (e) L2 queue uses a non-preemptive priority scheduling algorithm. A thread in L2 queue won’t preempt other threads in L2 queue; however, it will preempt thread in L3 queue. If two threads enter the L2 queue with the same priority, either one of them can execute first. (f) L3 queue uses a round-robin scheduling algorithm with time quantum 100 ticks (you should select a thread to run once 100 ticks elapsed). (g) An aging mechanism must be implemented, so that the priority of a process is increased by 10 after waiting for more than 1500 ticks. (Note: When the thread turns into running state, the waiting time should be reset). (h) The operations of preemption and priority updating MUST be delayed until the next timer alarm interval in alarm.cc Alarm::Callback. 2-2. Add a command line argument -ep for nachos to initialize priority of process. E.g., the command below will launch 2 processes: test1 with initial priority 40, and test2 with initial priority 80. $ ../build.linux/nachos -ep test1 40 -ep test2 80 2-3. Add a debugging flag z and use the DEBUG(‘z’, expr) macro (defined in debug.h) to print following messages. Replace {…} to the corresponding value. (a) Whenever a process is inserted into a queue: [A] Tick [{current total tick}]: Thread [{thread ID}] is inserted into queue L[{queue level}] (b) Whenever a process is removed from a queue: [B] Tick [{current total tick}]: Thread [{thread ID}] is removed from queue L[{queue level}] (c) Whenever a process changes its scheduling priority: [C] Tick [{current total tick}]: Thread [{thread ID}] changes its priority from [{old value}] to [{new value}] (d) Whenever a process updates its approximate burst time: [D] Tick [{current total tick}]: Thread [{thread ID}] update approximate burst time, from: [{ti-1}], add [{T}], to [{ti}] (e) Whenever a context switch occurs: [E] Tick [{current total tick}]: Thread [{new thread ID}] is now selected for execution, thread [{prev thread ID}] is replaced, and it has executed [{accumulated ticks}] ticks • Rules: (you MUST follow the following rules in your implementation) (a) Do not modify any code under the machine folder (except for Instructions 2. below). (b) Do NOT call the Interrupt::Schedule() function from your implemented code. (It simulates the hardware interrupt produced by hardware only.) (c) Only update approximate burst time ti (include both user and kernel mode) when the process changes its state from running state to waiting state. In case of running to ready (interrupted), its CPU burst time T must keep accumulating after it resumes running. (d) The operations of preemption and rescheduling events of aging must be delayed until the timer alarm is triggered (the next 100 ticks timer interval). (e) Due to rule (d), the below example is an acceptable solution: 2 threads x, y are waiting in the L3 queue, and thread x started executing at ticks 20. At ticks 100, the timer alarm was triggered and hence caused the rescheduling. So x left the running state and y started running. • Instructions 1. Copy your code for MP2 to a new folder. $ cp -r NachOS-4.0_MP2 NachOS-4.0_MP3 2. To observe scheduling easily by PrintInt(), change ConsoleTime to 1 in machine/stats.h. const int ConsoleTime = 1; 3. Comment out postOffice at Kernel::Initialize() and Kernel::~Kernel() in kernel.cc. ◦ postOfficeIn = new PostOfficeInput(10); ◦ postOfficeOut = new PostOfficeOutput(reliability); ◦ delete postOfficeIn; ◦ delete postOfficeOut; 4. Test your implementation, try different p1 and p2. (Appendix A provides some examples) $ cd NachOS-4.0_MP3/code/test $ cp /home/os2023/share/hw3t{1,2,3}.c ./ ◦ cat /home/os2023/share/MP3_Makefile >> Makefile ◦ make hw3t1 hw3t2 hw3t3 ◦ ../build.linux/nachos -ep hw3t1 -ep hw3t2 • Grading 1. Implementation correctness – 56% (a) Pass all test cases. (b) Correctness of working items. (c) Your working directory will be copied for validation after the deadline. 2. Report – 20% (a) Cover page including team members, team member contribution. (b) Explain the code trace required in Part II-1. (c) Explain your implementation for Part II-2 in detail. (d) Upload to iLMS with the filename MP3_report_.pdf 3. Demo – 24% (a) Demonstrate your implementation, and answer questions from TAs in 20 minutes. (b) Some random test cases will be used for correctness verification. 4. Plagiarism (a) NEVER SHOW YOUR CODE to others. (b) If the codes are similar to other people (including your upperclassman) and you can’t answer questions properly during the demo, you will be identified as plagiarism. Appendix A Note that the sample test case may have too little loop to trigger the aging mechanism. You can change the test case code by yourself. $ ../build.linux/nachos -ep hw3t1 0 -ep hw3t2 0 #L3 $ ../build.linux/nachos -ep hw3t1 50 -ep hw3t2 50 #L2 $ ../build.linux/nachos -ep hw3t1 50 -ep hw3t2 90 #L2 $ ../build.linux/nachos -ep hw3t1 100 -ep hw3t2 100 #L1 $ ../build.linux/nachos -ep hw3t1 40 -ep hw3t2 55 #L3 → L2 $ ../build.linux/nachos -ep hw3t1 40 -ep hw3t2 90 #L3 → L2 $ ../build.linux/nachos -ep hw3t1 90 -ep hw3t2 100 #L2 → L1 $ ../build.linux/nachos -ep hw3t1 60 -ep hw3t3 50 #L2 Appendix C x86 registers (32bit) Register Description eax, ebx, ecx, edx, esi, edi general purpose registers esp stack pointer ebp base pointer x86 instructions (32bit, AT&T) Instruction Description movl %eax, %ebx move 32bit value from register eax to register ebx movl 4(%eax), %ebx move 32bit value at memory address pointed by (the value of register eax plus 4), to register ebx ret set CPU program counter to the memory address pointed by the value of register esp pushl %eax subtract register esp by 4 (%esp = %esp – 4), then move 32bit value of register eax to the memory address pointed by register esp popl %eax move 32bit value at the memory address pointed by register esp to register eax, then add register esp by 4 (%esp = %esp + 4) call *%eax push CPU program counter + 4 (return address) to stack, then set CPU program counter to memory address pointed by the value of register eax x86 calling convention (cdecl) Item Description Caller passes function parameters Caller pushes the arguments to stack in the descending order. Callee reads the arguments from the memory address pointed by Callee catches function parameters (register esp + 4) in the ascending order. By the way, the value of memory address pointed by register esp is the return address described above (call instruction). Function parameters cleaning up Caller is responsible for cleaning up the arguments (pop).

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== Data/Function Design ==

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10910EECS204001 Data Structure HW1-Linked List

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10910EECS204001 Data Structure HW2-Elementary arithmetic

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